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Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
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Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Test Driven Development for FPGA Designs
Halász, Dávid ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Tato bakalářská práce popisuje, jak může být princip TDD uplatněn u hardware, převážně pro vývoj FPGA. Je popsána důležitá teorie pro pochopení kontextu. Na referenčním návrhu jsou představeny některé dostupné a užitečné verifikační nástroje. Jeden z těchto nástrojů byl vybrán a pomocí TDD byl vytvořen a úspěšně otestován návrh komunikačního modulu SPI.
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Measurement of GNSS receiver accuracy
Čepl, Miroslav ; Gábrlík, Petr (referee) ; Jílek, Tomáš (advisor)
In this thesis a new method of determining an accuracy of a GNSS receiver is presented. First, a research of basic GNSS systems and a description of receiver accuracy is performed. Subsequently, the method of measuring the accuracy with the focus on RTK mode is proposed. A measuring jig is designed and manufactured. After verifcation of jig accuracy, a measurement of three dierent antennas is performed for subsequent comparison of basic characteristics. The work also contains instructions for operating the measuring jig.
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Post Quantum Cryptography on FPGA
Gyõri, A. ; Smékal, D.
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation. The issue of postquantum cryptography and the VHDL programming language used to describe the functionality of the hardware was studied. The acquired knowledge was transformed into a functional simulation of all parts of the algorithm. All these parts have already been implemented separately, so that the functionality of every single part can be separately approached. These parts are key generation, encapsulation and decapsulation. After successful simulation. These parts will be synthetised and implemented to FPGA board NEXYS A7.
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Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Test Driven Development for FPGA Designs
Halász, Dávid ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Tato bakalářská práce popisuje, jak může být princip TDD uplatněn u hardware, převážně pro vývoj FPGA. Je popsána důležitá teorie pro pochopení kontextu. Na referenčním návrhu jsou představeny některé dostupné a užitečné verifikační nástroje. Jeden z těchto nástrojů byl vybrán a pomocí TDD byl vytvořen a úspěšně otestován návrh komunikačního modulu SPI.
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Measurement of GNSS receiver accuracy
Čepl, Miroslav ; Gábrlík, Petr (referee) ; Jílek, Tomáš (advisor)
In this thesis a new method of determining an accuracy of a GNSS receiver is presented. First, a research of basic GNSS systems and a description of receiver accuracy is performed. Subsequently, the method of measuring the accuracy with the focus on RTK mode is proposed. A measuring jig is designed and manufactured. After verifcation of jig accuracy, a measurement of three dierent antennas is performed for subsequent comparison of basic characteristics. The work also contains instructions for operating the measuring jig.
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